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Design of complementary metal oxide semiconductor inverter

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Author Affiliations

  • 1Department of Electronics and Communication Engineering, College of Science and Technology Rinchending, Phuntsholing, Bhutan
  • 2Department of Electronics and Communication Engineering, College of Science and Technology Rinchending, Phuntsholing, Bhutan
  • 3Department of Electronics and Communication Engineering, College of Science and Technology Rinchending, Phuntsholing, Bhutan

Res. J. Recent Sci., Volume 7, Issue (7), Pages 31-34, July,2 (2018)

Abstract

Power MOSFET IRF9140 and IRF150 from OrCAD library were used to design the CMOS inverter. Keeping their size in the ratio of 2:1 the design and evaluations are carried out through simulation in OrCAD capture environment. The inverter circuit is optimized to yield the optimal noise margin and time delay response. The evaluation presents the analysis of voltage transfer characteristics and its transient response. Through the evaluation of voltage transfer characteristics, high noise margin of 4.80V and low noise margin of 4.56V is achieved. The evaluated maximum power dissipation is 48W. The evaluation of transient response resulted into the rise and fall time delay of 0.057µS and 0.048µS. The paper presents the detailed evaluation of power MOSFET based CMOS inverter.

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