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A Novel NOC Architecture for SoC based Ultra Lightweight Crypto-Processor Using Present and Katan Algorithm

Author Affiliations

  • 1Sathyabama University, Chennai, INDIA
  • 2 Department of EEE, RMD Engineering College, Chennai, INDIA

Res. J. Engineering Sci., Volume 3, Issue (2), Pages 6-11, February,26 (2014)

Abstract

The performance computation of the Crypto-processor implemented on SoC platform is research of interest now. The traditional buses or wires have the problem of scalability, complexity and timing, from here we target this point and present a novel Network On Chip (NOC) architecture to overcome the cons. Network On Chip (NOC) consists of storage and I/O resources interconnected by network of switches for network computation. Two ultra lightweight cryptographic algorithms are presented in this paper namely PRESENT and KATAN. It is developed using Altera Cyclone IV E. The NOC architecture consists of different topology, switching and routing techniques based efficiency requirements. Finally the computed efficiency for the processor running at 330 MHz and taking 5.047 sec for computation using 0.323 mm2 cell area in 180 nm technology.

References

  1. Advances in Ultralightweight Cryptography for Low-cost RFID Tags: Gossamer Protocol Pedro Peris-Lopez, Julio Cesar Hernandez-Castro, Juan M. E. Tapiador, and Arturo Ribagorda (2009)
  2. W.J. Dally and B. Towles, Route Packets, Not Wires: On-Chip Inteconnection Networks, in the 38th annual Design AutomationConference, 684-689 (2001)
  3. Guerrier P. and Greiner A., A Generic Architecture for On-Chip Packet-Switched Interconnections," in Design, Automation and Test in Europe (DATE), 250-256 (2000)
  4. S. Bell et al., "TILE64 Processor: A 64-Core SoC with Mesh Interconnect," Solid-State Circuits Conference, 2008. Digest of Technical Papers. IEEE International, 88-598 (2008)
  5. S. Vangal et al., An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS, Solid-State Circuits Conference, 2007. Digest of TechnicalPapers. IEEE International, 98-589 (2007)
  6. S. Panasenko and S. Smagin. Energy-efficient cryptography: application of KATAN. SoftCOM 2011, 19 International Conference on Software, Telecommunications and Computer Networks. Split – Hvar – Dubrovnik, September 15-17, 2011, Proceedings (SS2 – Special Session on Green Networking) (2011)
  7. E. Volte. CRUNCH. A SHA-3 Candidate. // Available at http://www.voltee.com – 27 February 2009 (2009)
  8. E. Rijpkema, K. Goossens, A. Radulescu, J. Dielissen, J. van Meerbergen, P. Wielage and E. Waterlander, Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip, IEE Proc. Computers and Digital Techniques,150(5), 294-302 (2003)
  9. M. Panades, A. Greiner and A. Sheibanyrad, A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach, Proc. the 1st Int’l Conf. and Workshop on Nano-Networks), 1-5, (2006)