6th International Young Scientist Congress (IYSC-2021) and workshop on Intellectual Property Rights on 8th and 9th May 2021.  10th International Science Congress (ISC-2020) will be Postponed to 8th and 9th December 2021 Due to COVID-19.  International E-publication: Publish Projects, Dissertation, Theses, Books, Souvenir, Conference Proceeding with ISBN.  International E-Bulletin: Information/News regarding: Academics and Research

Performance Optimization of HVD:An Error Detection and Correction Code

Author Affiliations

  • 1 Department of Electronics and Communication, Acropolis Institute of Technology and Research, Indore, INDIA

Res. J. Engineering Sci., Volume 2, Issue (6), Pages 25-29, June,26 (2013)

Abstract

Several EDAC techniques have been proposed and employed to effectively detect and correct errors introduced during data transmission over a communication channel or at the destination domain during storage. Some of these techniques can detect: only single error, all unidirectional errors, only burst errors, any bit in a data packet is change from one to zero or zero to one it means error is occur in same, errors with known locations assume a code is correct if the error location are known or cannot detect errors which appear in the same location in a pair of message codes. Coding techniques that detects and correct errors are more precise at detecting error locations and correcting them, however if more than one error occur, it becomes a challenge to detect all errors in a data frames and converted back its original form . In this paper, an advanced error detection and correction method to protect against errors is proposed. This method is based on 4D parities checking. This method, which is named HVD, provides very high detection coverage rate that can correct up to three flips in a data bit. The performance of HVD is optimize in comparison with the following coding techniques: CRC, Hamming codes. An independent design platform is utilized for the simulation by Xilinx 8.1 using ModelSim SE-EE 5.4a which shows a significant reduction in uncorrected errors during data transmission. The efficient performance of HVD makes it a more applicable coding technique for communication, data transmission, different protocols and other application.

References

  1. Anlei Wang, Member, IEEE, and Naima Kaabouch, Member, IEEE. “FPGA Based Design of a Novel Enhanced Error Detection and Correction Technique, 25-29 (2008)
  2. Behrouz A. Forouzan Data Communication and networking, 2nd edit. Tata McGraw Hill (2011)
  3. Clarke K.P., Reed-Solomon error correction, Research and development British Broadcasting Corporation, WHP 031 BBC (2002)
  4. McAuley A.J., Weighted sum codes for error detection and their comparison with existing codes, IEEE/ACM Trans. on Networking, 2(1), 16–22 (1994)
  5. Feldmeier D.C., Fast Software Implementation of Error Detection Codes, IEEE/ACM Trans. Networking 3(6),640-651 (1995)
  6. Berrou, C., Glavieux A. and Thitimajshima P., Near Shannon limit error-correcting coding and decoding: Turbo-codes International Conference on Communications, 1064-1069 (1993)
  7. Baicheva T., Dodunekov S. and Kazakov P., On the cyclic redundancy-check codes with 8-bit redundancy, Computer Communications,21, 1030–1033 (1998)
  8. Kazakov P., Fast calculation of the number of minimum-weight words of CRC codes, IEEE Transactions on Information Theory, 47(3), 1190–1195 (2001)
  9. Koopman P., 32-bit cyclic redundancy codes for internet applications, in International Conference on Dependable Systems and Networks, June 23–26, 459–468 (2002)
  10. Mostafa Kishani, Hamid R. Zarandi, Hossein Pedram, Alireza Tajary, Mohsen Raji and Behnam Ghavami, HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors, (2011)